Description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
TechLead– Verification Methodology / CAD / Automation Engineer
Experience - 6–12 years
Job Summary
We are looking for a Tech Lead – Verification Methodology/CAD/Automation Engineer to drive verification infrastructure, methodology, automation, and productivity across IP and SoC verification teams.
The candidate will build scalable verification frameworks, automate verification workflows, improve regression infrastructure, and partner with design verification teams to establish efficient and reusable methodologies.
Key Responsibilities
- Own and drive verification methodology and infrastructure across projects.
- Develop scalable frameworks for simulation, regression, coverage, debug, and verification signoff.
- Build and maintain verification CAD/automation flows.
- Develop automation scripts and tools using Python, Tcl, Perl, Shell, and/or C++.
- Automate test generation, compilation, regression execution, result collection, coverage analysis, and reporting.
- Develop infrastructure for large-scale UVM/SystemVerilog verification environments.
- Improve simulation and regression turnaround time through parallelization and optimization.
- Integrate simulation, lint, CDC/RDC, formal, coverage, and other verification tools into common workflows.
- Develop dashboards and metrics for verification quality, coverage, regression health, and project status.
- Debug infrastructure and tool-flow issues and provide rapid support to verification teams.
- Establish reusable verification components, scripts, libraries, and methodology guidelines.
- Drive adoption of best practices across multiple verification teams.
- Evaluate new verification technologies and tools and recommend improvements.
- Work closely with EDA vendors to troubleshoot tool issues and improve flows.
- Support migration and integration of new EDA tool versions and methodologies.
- Develop documentation and training for verification teams.
- Mentor verification CAD/methodology engineers and provide technical leadership.
Required Technical Skills
- Strong experience in verification methodology, CAD, and automation.
- Strong programming/scripting skills in Python, Tcl, Perl, Shell, and preferably C/C++.
- Strong understanding of SystemVerilog/UVM.
- Experience with simulation tools such as VCS, Xcelium, Questa, or equivalent.
- Experience building and maintaining regression infrastructure.
- Strong knowledge of coverage collection and analysis.
- Understanding of verification flows including:
- Simulation
- UVM
- Lint
- CDC/RDC
- Formal
- Code/functional coverage
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